Sharp FO-6700 Service Manual download pdf (Page 67)

FO-6700U

FO-67DL

5 – 11

HD813201F (IC26) Terminal descriptions

Code Terminal No. I/O Function

68/80 56 I If this terminal is at "low" level, it indicates that MPU of system 88 is connected

to IDP201. "High" level indicates that MPU of system 80 is connected.

A0 57 I

A1 54

A2 55

D0 64 I/O,

D1 62

Three-state output

D2 65

D3 63

D4 67

D5 66

D6 68

D7 69

CS 44 I Chip select (chip select terminal). When the terminal is at "low" level, it indicates

that MPU gets an access to the internal register of IDP201.

DS 45 I Data strobe (data strobe terminal). Connect φ2 clock pin of MPU of system 88 or

RD pin of MPU of system 80.

R/W 42 I Read/write (read/write terminal). Connect R/W pin of MPU of system 88 or WR

pin of MPU of system 80.

RESET 59 I Reset element. If the signal of "low" level is input to the terminal, IDP201 will be

initialized.

IRQT 58 O Interrupt request (interrupt request terminal). When the signal of "high" level is

output, IDP201 requests the interrupt process for MPU.

The factor of the interrupt is the end of the command process, the end of DMA

transfer, occurrence of an error during demodulation or the receiving of RTC

code.

MPU reads IRR (interrupt request register) which is one of the internal registers

of IDP201, and can know the factor of the interrupt. When MPU reads IRR,

IRQT becomes "low" level.

(For details of IRR, refer to "8.1.2 Interrupt request register".)

DRQTO 47 O DMA Request Output (DMA request output terminal). In the following cases,

DMA transfer can be requested for DMAC by turning DRQTO to "high".

(1) During coding, a code of 1 byte or more is stored in E-FIFO.

(2) During decoding, an empty area of 1 byte or more is present.

(3) During data transfer between the system bus and image bus, DBR is

read to read or write.

DACKI 46 I DMA Acknowledge Input (DMA acknowledge input terminal)

The response signal for DRQTO is input. If DACKI becomes "low" level during

coding or decoding, the access is given to E-FIFO or D-FIFO. If DACKI becomes

"low" level during data transfer between system bus and image bus, the access

is given to DBR.

Don’t make CS and DACKI "low" at the same time.

BRQT 52 O Bus Request (Bus request terminal). IDP201 outputs the signal of "high" level

from BRQT, and IDP201 requests the bus master for the device which can

become another bus master on the image bus. If any other device which can

become the bus master on the image bus, BRQT becomes the NC pin.

BACK 48 I Bus Acknowledge (bus acknowledge terminal). The response signal for BRQT is

input. If the signal of "low" level is input to BACK, it indicates that it is approved

for IDP201 to become the bus master of the image bus. If any other bus master

which can become the bus master is not present except IDP201, fix this terminal

at "low".

MAEN 76 O Memory Address Enable (Memory address enable terminal). IDP201 outputs the

signal of "low" level from MAEN to declare that it becomes the bus master of the

image bus. When MAEN is at "high", the three-state output which is connected

to the image bus becomes all into the high impedance state.

Addresses 0 thru 2 (address terminals). It is connected to the low-order 3 bits of

the system address bus, and MPU is used to get an access to the internal

Data 0 thru 7 (data terminals). They are connected to the system data bus for

bidirectional data transfer between MPU and IDP201. MPU can read and write

the internal register of IDP201.

1 2 ... 62 63 64 65 66 67 68 69 70 71 72 ... 191 192

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Sharp FO-6700 Service Manual Page 67

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