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Sharp FO-6700 Service Manual Page 64

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FO-6700U
FO-67DL
5 – 8
(8) Gate Array (B) Block
The block is composed of the Gate Array (B) and SRAM (2 KByte).
1) LR38292(IC22) ... pin-160, QFP (Gate Array B)
The device has the following functions.
Printing Data Process
The image data of the page memory for printing is converted into
400 dpi, and the smoothing and contracting processes are applied.
Printer (PCU) Interface
The control of resetting and so on to PCU and the image data proc-
essed in Item above are synchronized with the signal (HSYNC)
from PCU and are transmitted to PCU in the serial mode.
DMA Controller
(a) The binary-coded data of the draft transmitted in the serial mode
from the Gate Array (A) LZ9FJ59(IC8) and read with the scanner
are transmitted to the page memory.
(b) The image data which will be printed are read from the page
memory, and the process is applied to transmit the data to
PCU in the serial mode.
CODEC (HD813201F) Interface
(a) The timing is controlled for CPU to get an access to CODEC.
(b) The timing is controlled for CODEC to get an access to the page
memory.
DRAM Controller
Since DRAM is used for the page memory, and the address, RAS
and CAS are controlled and refresh-controlled.
Panel Interface
The key input detection on the operation panel, LED lighting control
and LCD display control are executed.
2) LH5116NA-10 (IC30) -- pin-24, SOP (16-Kbit SRAM)
This SRAM is a line memory for the printing data process (resolution
power conversion, smoothing and contracting to 404 dpi) of the Gate
Array (B).
LR38292 (IC22) Terminal descriptions
Pin Name I/O Function
20 VCC Power supply
62 VCC
100 VCC
142 VCC
16 GND Ground
21 GND
35 GND
48 GND
61 GND
78 GND
87 GND
101 GND
125 GND
134 GND
143 GND
65 MANRESB O Manual reset signal
66 RESETB I Reset signal
89 A5 I Address signal on the system side
90 A4
91 A3
92 A2
93 A1
70 D15 I/O Data bus signal on the system side
71 D14
72 D13
73 D12
74 D11
75 D10
76 D9
77 D8
79 D7
80 D6
81 D5
82 D4
83 D3
84 D2
85 D1
86 D0
88 CSB I
Chip select signal of gate array LR38292
97 RDB I Read signal on the system bus side
98 WRB I Write signal on the system bus side
115 SHCK0B O
Reversion output of clock (SHCK) from
CPU
116 SHCK I Clock (19.6 MHz) from CPU
95 GAINTB O
Interrupt request signal to CPU of gate
array LR38292
94 CDCINTB O
Reversion output (to CPU) of interrupt
request signal from HD813201F
96 DREQ0B O Reversion output (to CPU) of DMA
transfer request signal from HD813201F
99 RSTCDCB O Reset signal to HD813201F (Default:
Low)
102 CDCINT I
Interrupt request signal from HD813201F
103 BRQT I Bus right request signal of image bus
from HD813201F
104 BACKB O
Bus right permission signal of image bus
to HD813201F
105 DRQ0 I DMA transfer request signal from
HD813201F
106 DACK0B O
Acknowledge signal of DMA transfer to
HD813201F
107 CSCDCB I Chip select signal to HD813201F
108 MDENB I
Data enable signal of image bus from
HD813201F
109 READY O
Ready signal of image bus access to
HD813201F
110 MAS I
Address strobe signal of image bus of
HD813201F
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