Sharp FO-6700 Service Manual download pdf (Page 60)

FO-6700U

FO-67DL

5 – 4

(2) Image Memory Block

This block is composed of Memory PWB circuit.

Refer to [4] Circuit description of Memory PWB for the details.

(3) Back-up Circuit Block

This block is composed of SRAM (256KByte), Flash Memory (1MB)

and RTC (SM8578BV).

1) BS62LV1024SC-70 (IC15, IC21) ... pin32, SOP

This device is a 1Mbit SRAM.

The setting of receiving mode, optional setting content, soft switch con-

tent and dairy data are stored. Even if the power supply of the main

body is turned off, it is backed up with a lithium battery.

2) LH28F800SUT-70 (IC10) ... pin56, TSOP

This device is a 16Mbit flash memory of a nonvolatile type whose con-

tent does not volatilize even if power is turned off.

And it is stored the several initial data, as the telephone list etc.

3) SM8578BV (IC1): pin-8, SOP (Real Time Clock IC)

It is oscillated with the quartz oscillator of 32.768KHz, and the clock and

calendar functions are provided. Even if the power supply of the main

body is turned off, it is backed up with lithium battery. This device ex-

ecutes the clock-synchronous type serial communication with the Gate

Array (A), and CPU can know the time and date through the Gate Array

(A).

(4) Image Signal Process Block

The CIS is driven by the LSI (LC82103), and the output video signal

from the CIS is input into the LC82103 through the amplifying circuit.

The ADC and buffer are provided in the LC82103, and the digital image

processing is performed.

(5) Speaker Amplifier Block

The speaker amplifier monitors the line under the on-hook mode, out-

puts the buzzer sound generated from the SH7021, ringer sound, DTMF

generated from the Line Control PWB, and line sound.

(6) Reading Process and Mechanical Control Block

1) Mechanical Control Block

The Mechanical Control Block is mainly composed of the Gate Array (A)

(IC8: LZ9FJ59) to control the following.

(a) Sending Motor Control

The revolution speed and timing of the Sending Motor are controlled to

output the control signals to the Motor Driver (IC7).

(b) End Stamp (OPTION:FO-45VS) and LED Lamp Control

On/off of the End Stamp and LED Lamp is controlled with the

software.

Fig. 2

(7) Gate Array (A) Block

This block is mainly composed of the Gate Array (A) (IC8: LZ9FJ59),

and has the following functions.

Mapper

Mapping is executed in the memory area of the memories, Gate

Array (B), Modem, CODEC and Reading Process LSI (LC82103).

Mechanical Control Block

Refer to 1) Mechanical Control Block of 2-(6) Reading Process

and Mechanical Control Block.

IC Interface for clock

Writing and reading to IC (IC1: SM8578BV) for clock is executed

in the clock-synchronous type serial transfer mode.

CIS

VIDEO

SIGNAL

AMPLIFIER

CIRCUIT

LC82103

(IC5)

CLOCK

VREF+

VREF—

1 2 ... 55 56 57 58 59 60 61 62 63 64 65 ... 191 192

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Sharp FO-6700 Service Manual Page 60

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