Sharp AR-168N Specifications Page 134

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AR-168N/168L CIRCUIT DIAGRAM 14 - 1
[14]CIRCUIT DIAGRAM
1. MCU PWB
MCU PWB (CPU section)
C24
0.1u
C4
12p
R11 10kJ
R5
0J
BR20
33J
1
2
3
4
8
7
6
5
R18
11kF
C25
47p
R20
10kF
BR21
33J
1
2
3
4
8
7
6
5
R19
3.3kJ
IC2
HD6412321VF25(H8S/2321)
P35
/
P34
/
P33
/
P32
/
P31
P30
/
PD
7
PD
6
PD
5
PD
4
P
D
PD
2
P
D
P
D
P
E
P
E
P
E
P
E
P
E
P
E
P
P
E
AVcc
103
Vref
104
P40/AN0
105
P41/AN1
106
P42/AN2
107
P43/AN3
108
P44/AN4
109
P45/AN5
110
P46/AN6/DA0
111
P47/AN7/DA1
112
AVss
113
Vss
114
P17/PO15/TIOCB2/TCLKD
115
P16/PO14/TIOCA2
116
P15/PO13/TIOCB1/TCLKC
117
P14/PO12/TIOCA1
118
P13/PO11/TIOCD0/TCLKB
119
P12/PO10/TIOCC0/TCLKA
120
P11/PO9/TIOCB0/DACK1
121
P10/PO8/TIOCA0/DACK0
122
MD0
123
MD1
124
MD2
125
PG0/CAS
126
PG1/CS3
127
PG2/CS2
128
PG3/CS1
1
PG4/CS0
2
Vss
3
NC
4
VCC
5
PC0/A0
6
PC1/A1
7
PC2/A2
8
PC3/A3
9
Vss
10
PC4/A4
11
PC5/A5
12
PC6/A6
13
PC7/A7
14
PB0/A8
15
PB1/A9
16
PB2/A10
17
PB3/A11
18
Vss
19
PB4/A12
20
PB5/A13
21
PB6/A14
22
PB7/A15
23
PA0/A16
24
PA1/A17
25
PA2/A18
26
PA3/A19
27
Vss
28
PA4/A20/IRQ4
29
PA5/A21/IRQ5
30
PA6/A22/IRQ6
31
PA7/A23/IRQ7
32
P67/
/
CS7 IRQ3
33
P66/
/
CS6 IRQ2
34
Vss
35
Vss
36
P65/IRQ1
37
P64/IRQ0
38
P53/ADTRG
102
P52/SCK2
101
Vss
100
Vss
99
P51/RxD2
98
P50/TxD2
97
PF0/BREQ
96
PF1/BACK
95
PF2/
/WAIT/BREQO
LCAS
94
PF3/LWR
93
PF4/HWR
92
PF5/RD
91
PF6/AS
90
VCC
89
PF7/0
88
Vss
87
EXTAL
86
XTAL
85
VCC
84
STBY
83
NMI
82
RES
81
WDT
OVF
80
P20/PO0/TIOCA3
79
P21/PO1/YICOB3
78
P22/PO2/TIOCC3
77
P23/PO3/TIOCD3
76
P24/PO4/TIOCA4
75
P25/PO5/TIOCB4
74
P26/PO6/TIOCA5
73
P27/PO7/TIOCB5
72
P63/TEND1
71
P62/DREQ1
70
P61/ /TEND0 CS5
69
Vss
68
Vss
67
P60/
/
DREQ0 CS4
66
Vss
65
R4 *3
BR22
33J
1
2
3
4
8
7
6
5
C1
*6
R13 10kJ
R2 *2
BR23
33J
1
2
3
4
8
7
6
5
IC4
M51957BFP
NC
8
GND
4
VCC
7
NC
1
IN
2
NC
3
Cd
5
OUT
6
BR24
33J
1
2
3
4
8
7
6
5
R7 *4
C381
22pF
R1
OPEN
C382
OPEN
C383
OPEN
C384
OPEN
X1
HC-49U/S
19.6608MHz
R22
10kJ
R21 33J
C22
0.1u
R8 33J
BR110
33J
1
2
3
4
8
7
6
5
IC1
P2010/PLL701-01
Xin
1
Xout
2
FS0
3
Vss
4
SSon
5
MODOUT
6
SR0
7
VDD
8
R12 10kJ
C3 *5
R3 *1
R6
0J
R10 100J
R337
33J
C23
OPEN
C2
0.1u
R9 33J
C386
OPEN
A0
A5
A2
A4
A11
A19
A13
A3
A8
A10
A7
A12
A16
A14
A18
A1
A15
A17
A6
A9
CPUCLK(NC)
/TRANSST
SPFMT0
/SCANSP
SPFMT1
SPFMT2
/SCANST
SPFMT3
/STBY
ES_CMD
RD
/ESS_RDY
/ESC_RDY
HWR
/PRINTST
LWR
ESS_TS
RESETOUT1
NMI
/WDT
OVF
/CS0#
/CS1#
/CS2#
/CS3#
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
/PRINTST
/RESET0
/ASIC_RST
/ES_PAGE
MSU_ST1
SPFMT0
SPFMT2/MIRCNT
(SIN2)
SPFMT1
/TRANSST
(KEYIN)
PMCLK
RTH
SPFMT3
/SCANSP
PSL
/SCANST
(SIN3)
(SIN1)
ESS_TS
/ESC_RDY
ES_CMD
/HWR
/LWR
/ESS_RDY
/RD
SELIN3
SELIN2
SELIN1
/RESET1
/CS3
/CS2
/CS1
/CS0
Spreading Range :
+/- 1.25%
R4(*3)
When IC1 is, mounted NOT mounted
OPEN 0J
R3(*1)
OPEN 680J
R7(*4)
22J OPEN
R2(*2)
0J OPEN
C3(*5)
C1(*6)
22pF
22pF
15pF
15pF
*R2,R3,C1, and C3 are tentative
(2-D2)
(2-E3)
(2-E3)
(2-E3)
(4-C3)
(4-C2)
(4-C3)
(4-C3)
(2-D1)
(5-B2)
(2-C4)
(8-A2)
(13-B2)
(4-D4)
(4-D4)
(4-C3)
(4-D4)
(5-E3)
(4-D4)
(8-A1)
Reset IC
(4-C2)
(8-A3)
(13-B2) (2-C1)
(4-C2)
(3-A2)
(4-A2)
(2-C1)
(4-C2)
(3-A2)
(8-A3)
(8-A2)
(8-A2)
(9-B2)
A
A
B
B
C
C
4
3
2
1
14_CIRCUTDIAGRAM.fm 1 ページ 2005年11月18日 金曜日 午後7時14分
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