3-2. Main CPU and I/O port
MZ3500
A2
YO
AS
B
M
A4
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A
1
A5
Y2
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A6
G2A
Y3
A7
C
P
lORQ
G2B
Y4
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Y5
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G1
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Y7
74 LS138
This paragraph discusses main CPU I/O
Connector port select and addressing.
I FC2 The address output from the main CPU
I is decoded in the 74LSI38 to create the
I select signal.
I Table below describes address map and
[ signal functions.
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