Sharp MZ-3500 User Manual Page 34
- Page / 116
- Table of contents
- BOOKMARKS
Rated. / 5. Based on customer reviews
M Z 3500
4Æ. Master slice LSI (CSP-1) SP6102C 002 signal description
Pm No.
Prionly
IN/OUT
Function
Signal Name
1
HSY.
IN
Horizontal synchronizing signal from the GDCl Also, it becomes the refresh timing signal in the
dynamic RAM mode.
2 NABC
IN
Input from the UPO7220 GOC1. When the GDCl is in the character display mode, the attribute,
blinking timing and line counter clear signals are multiplexed.
3
CSR IN
Input from the GDC1 which is the cursor display input when the GDCl is in the character display
mode.
4 ~ 6
ASO - AS2 IN
Address bus input from the sub-CPU.
ABO = ASO, ABl = AS1, AB2 = AS2
7 ~ 9 DSO - DS2 IN
Data bus input from the sub-CPU.
DBO = DBO. DB1 = DB1, DB2 = DB2
10
G2 OUT
Green image output to the CRT2.
11 NWRO
IN
CSP1 I/O port select signal (OUT #5X)
12 "Nve IN
Input of The blue image from the graphic RAM(A) and (B).
13 NVR
IN
Input of the red image from the graphic RAM (B), (C), and (D).
14
NVB
IN
Input of the green image from the graphic RAM (E) and (F).
15 FYD2 IN
Input of the graphic RAM parallet/senal conversion 1C 74LS166 shift out clock.
(Used to latch the image data in CSPI.)
16-18 AT2 - AT4 IN
Attribute data input from the 2114A-1 attribute RAM.
fAT-2 — Horizontal tme/R ')
AT-3 ~ Reverse/G 1
[aT-4- Blink J
19
CH
IN
Input of character display data signal.
20. 21 GND
IN
OV supply
22
DSP2
IN
Input of display timing signal supplied from the CSP-2. (BLINK signal from the GDC2 is delayed by
two flipflop intervals in the CSP-2 to créât this signal.)
23
VID2
OUT
VIDEO output to CRT2.
24
LCO
OUT
Character CG line counter output.
(Becomes address input to the CG when LCO = CG address AO.)
25 ATI
IN
Attribute data input (vertical Ilne/B) from the 2114A-1 attribute RAM.
26-28
LC1 - LC3 OUT
Character CG line counter output.
(LC1 = A1, LC2 = A2, LC3 = A3CG = A3)
29
NCL4 OUT
Character CG output data latch timing.
30
HSYO OUT
CRT1,2 horizontal synchronizing signal
31
RA40
OUT
The signal that turns high level when the 400-raster CRT is m connection. LDA, 01 H OUT??56
32
VIDI
OUT
VIDEO output to the CRT1.
33
81 OUT
Blue image output to the CRT1.
34
R1 OUT
Red image output to the CRT1.
35
gT
OUT
Green image output to the CRTl.
36
SL1
IN
Character CG output parallel/serial converter IC 74LS166 shift load signal, and character CG address
latch signal input. (Used for the image data latch signal in the CSP-1 and horizontal synchronizing
signal delay flipflop clock.)
37
82 OUT
Blue image output to CRT2. ■
38
R2 OUT
Red image output to CRT2.
39
BLNK
IN
Erase signal from the GDC1 which becomes input at the following times.
1. Horizontal flyback period
2. Vertical flyback period
3. Period from the execution of the SYNC SET command to the execution of the DISP START
command.
4. Line drawing period
40
Vcc
IN
+5V supply.
39
- SERVICE MANUAL 1
- 1. SPECIFICATIONS 2
- Keyboard layout 3
- 1-3. MZ-1U02 3
- 1-4. MZ-IR03 4
- 1-6. MZ-1R06 5
- 1-7. MZ-1D07 6
- 2-1. SDO (INITIALIZE STATE) 8
- MAIN CPU 8
- M* )S V 1 M/} 9
- MZS.'tOO 10
- 2.3. SD2 (ROM based BASIC) 11
- Operational description 12
- 3. CPU AND MEMORY 13
- L© 'MTR ! 14
- 3-3. Sub CPU and I/O port 15
- 1) Block diagram 16
- ‘ VK IN MEMCKT MM I Mf 20
- 4. CRT DISPLAY 22
- X 25 lines screen.) 24
- For Model 3200 senes 26
- 4-2. Video RAM 27
- 5) Synchronize signal timing 30
- X : Y - 1 : 2 30
- X : Y : 1 : 1 31
- 'iBK byte 32
- (option I) 32
- 48K byte 32
- (option tl) 32
- M Z 3500 34
- CSP 2 Block Diagram 37
- 20 GND IN 38
- ASCII C.G. Structure 40
- 4 9. VSYNC 41
- ARIO = HI 42
- > FIFO Empty? 44
- [Explanation] 45
- Straight line drawing 46
- Whereas 46
- 5. MFD INTERFACE 47
- ^ 0 ^ 0 1 49
- 8) Data write procedure 50
- 5^. FDC (UPD765) 52
- UPD765 signal description 53
- 5-5. Data recording method 54
- <ITE DATA 55
- Write pulse [] fl d fl R 56
- Polarity inversion 56
- +5V RtAD DATA 57
- M -- 3.1 58
- ©"T 58
- Advanced 59
- Does not trace i l^is 59
- 5-11. Media format 60
- (Bbyles) 61
- 02 0\ FF FF 62
- ( 2KX 152 = 304K ) 63
- Stop bit 64
- 6-4. System switch functions 65
- 6-5. 8251AC controls 65
- 2) Data output control 66
- 3) Data input control 67
- 7-D0C># 68
- 3iil>CPU of Ni^ 70
- <i> 71
- 7 4. Data transfer timing 72
- 7-6. I/O port map 73
- 8. OTHER INTERFACES 74
- -<3 ri> 75
- MZ,"500 76
- DIP SW(A) 79
- 1. BLOCK DIAGRAM 80
- A. +5V and +12V supplies 80
- M 7,3500 81
- 3. Alarm circuit 82
- DESCRIPTION 83
- 10-2. Key search timing 84
- JLJl_JlJT_ri_rLJl 85
- Power ON 86
- START (5mS) 86
- 11. SELF CHECK FUNCTIONS 87
- CD SDO bank alternation error 88
- 11-2. Sub-CPU side 89
- .8 test the 90
- 20 lines 90
- /<.y ^ Jf -y > K W 91
- 8) ROM-IPL 92
- S3Si-54Kl=-.*- • 93
- 12. IPL FLOW CHART 96
- MAIN CPU IPL FLOW CHART 2/2 97
- 12 2. SUB CPU IPL FLOW CHART 98
- ■ I I Y Y TV 99
- IjJliJlJjljJljJLllLljLLJ 99
- LlJ LiJ LiJ Lei LiJ LLl LiJ 99
- LJLeJ'LDliJLiJLLjLJLiJ 99
- Pi co vO co fO Pi 100
- Ч Г ^n UO 100
- ¿. ^ О 101
- Û. CM Û 101
- GUIDE LIST 102
- I'l Exteriors 103
- 1 Exteriors 104
- PWB & Fixing angles 105
- [3 Connector 106
- [4] Others 107
- 5 CPU PWB 107
- 5I CPU PWB 108
- U Power supply unit 108
- [6j Power supply unit 109
- П MZ1R06 (RAM board) 111
- SHARP CORPORATION 116
- Industrial Instruments Group 116
© 2020, manymanuals.com. All rights reserved. | 0.135 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comments to this Manuals