Sharp MZ-3500 User Manual

MZ-3500SERVICE MANUALCODE; OOZMZ 3500SM/EPERSONAL COMPUTERMODEL MZ-3500CONTENTSI1. Specifications...

ROM-IPL1. An 8KB ROM (2764 or mask ROM equivalent) is used for the ROM-IPL.2. When the system reset signal turns from low to high

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MZ-3500PARTS GUIDE LIST

MZ-3500I'l ExteriorsNOPARTS CODEPRICERANKNEWMARKPARTRANKDESCRIPTION1CCABC1007ACZZ A Y DFront Cabinet assembly2GFTAFIOOIACZZ A E N DLid for Graphi

MZ-35001 Exteriors'31Litf'l

MZ-3500[2] PWB & Fixing anglesNOPARTS CODEPRICERANKNEWMARKPARTRANKDESCRIPTIONJKNBM0004PAZZ A C Nc Knob for V R2LANGS1006ACZZA FNcFixing angle lor

M2-3500[3 ConnectorNOPARTS CODEPRICERANKNEWMARKPARTRANKDESCRIPTION1OCNCP604IQCZZ AWCConnector7QCNCP484 IQCZZA TCConnector_3”6"OCNCWlOOlACZZA ZCCo

MZ-3500[4] OthersNO.PARTS CODEPRICERANKNEWMARKPARTRANKDESCRIPTION1RMEMR1004AC07 B ADMaster media9UBNDAl008CCZZA AD AC Cord band10SPAKA1003ACZZA Z NDPa

MZ-3500l5I CPU PWBNOPARTS CODEPRICERANKNEWMARKPARTRANKDESCRIPTION69VH;M74LS367-1A Hвю70VHiM74LS373-lAQв1C71VHiM74LS74/-1 A G В1C77VHiM74LS75/-1A Eв1C7

MZ-3500[6j Power supply unitNO,PARTS CODEPRICERANKNEWMARKPARTRANKDESCRIPTION250AE30121921// A CN BDiode (1S2076A-EEC) [D005]260AE30121921// ACNB Diode

MZ3500Operational description(1 ) As soon as the sub-CPU is started, it initializes the I/O port and waits for program transfer (IOCS

M2-3500[9. MZ1K02,1K03,1K04,1K05 (Key unit)11

MZ-3500lOÌ MZ1R03 (Graphic board)NOPARTS CODEPRICERANKNEWMARKPARTRANKDESCRIPTION1DUNTK1025ACZZ* *N EPWB unit2SPAKA1013ACZZA H NcPacking cushion3SPAKCl

MZ-3500IndexPARTS CODENO.PRICERANKNEWMARKPARTRANK: c ]CCABC 1 0 0 7 ACZ21- 1AYD[ D ]DUNT-1018ACZ21- 17♦ *NEDUNT- 1 0 3 5 ACZZP 17* ♦EDUNTK 1 0 2 5 ACZ

MZ-3500PARTS CODENOPRICERANKNEWMARKPARTRANKPARTS CODENOPRICERANKNEWMARKPARTRANKSPAKAl004ACZZ 9- 109AGDVH1HM4 7 2 1 1 4-15- 49 AU BSPAKA I 0 0 9 ACZZ T

MZ-3500fuPARTS CODENOPRICERANKNEWMARKPARTRANKVH1 416 4-15 0-H 5- 89A ZBn11- nA 2 BVH1 8 2 5 1 AC//-15- 90A Y 8VH 1 8 2 5 3////-15- 91B ABVHPGL3PR2//-1

MZ-3500PARTS CODENOPRICERANKNEWMARKPARTRANK0AE 3 0 1 2 0 5 2 4//6- 65 ACNc//6- 66 ACNcOAE 3 0 1 2 0 6 5 0//6- 44AGNcOAE 3 0 1 2 1 8 6 6//6- 36AN Nв0AE

SHARP CORPORATION Industrial Instruments Group Reliability & Quality Control Department Yamatokoriyama, Nara 639-11, Japan1983 January Printed in

2-4. SD3 (RAM based BASIC)SD3 is active when "SHARP BASIC" is ececuted via RAM. "SHARP BASIC" is loaded in RAM from the floppy dis

3. CPU AND MEMORY3-1. Block diagram1) Relation between MMR (Main Memory Mapper) and main memory.I

3-2. Main CPU and I/O portMZ3500A2YOASBMA4YiA1A5Y2NA6G2AY3A7CPlORQG2BY4uuY5¥TG1YGY774 LS138This paragraph discusses main CPU I/O Connector port select

3-3. Sub CPU and I/O portMZ3500AS6Y7ASS___2.BY6SUBAS4 1YSCPUAS7“c4GG2AY4Y33—G2BY2¥T6G1Y1YO74LSI38S07S0610 SOS.11 S04 12 S03.15 S0215 SOO-►gdc-iGra

3-4. Memory mapper (MMR) SP6102R-0011) Block diagramMZ350019 -

2) Memory mapper (MMR) SP6102R-001 signal descriptionMZ3500Pin No.1012PolaritySignal NameSTDO07A15A13IN/OUTININ/OUTINFunctionMain CPU DRAM output buff

M7-3S00Pin No.PolarityIN/OUT FunctionSignai Name32RF1BOUTMam CPU 128KB dynamic RAM output buffer (LS244) output enable signal.(RAM buffer 1)33RF2BOUTS

M/.3500Pm NoPolarity Signal NameIN/OUTFunction57 SYSR INSystem reset signal.Used to reset I/O port in the MMR.(System Reset)58FD3INInput from the syte

M 7 35001. SPECIFICATIONS1-1. Specification of the main unit (Model 35XX)Outline1) High speed processing using multi-CPU2) Built in mini floppy disk3)

M/3S00MAIN CPUI/O PORT IN MEMORY MAPPERADDKKSS-\7 A6 A5 A4 A3 A2 Al AO111110 01111110 11111111011111111HEXDHUSECEl)FEFFDIDOD7DO1)7U6D5D4D2D1DOD4D3D2D1

3-5. Memory (ROMIPL, RAMCOM, S RAM) select circuitMZ35001) ROM-IPL select by the main CPUAs ROM IPL turns to low level after power on addre

4. CRT DISPLAYy-/ rr-,^4-1. SpecificationDisplay memoryUst of fiigh resduiion CRT3KB (characu>-$l 96KB, max (graphtc iOptionUse of medium resolutio

Summary of video display specificationTable 1High resolution CRT (640 x 400 dots mode)Medium resolution CRT (640 x 200 dots mode)Type of monitorGreen

M7 35001) Character display 1.1. Screen structure, High resolution CRT CRT used , (640 x 400 dot)|| fH = 20 9KHz Character |! INewlfV = 47 3HzMedium

MZ 35006) Screen overlay and displaying on two independent CRT’sAs there are two video output channels it will be pos sible to display t

MZ35007) ASCII CGUses an 8KB MROM contains two patterns'640 X 400 dots (8x16 dots) and 640 x 200 dots (8x8 dots)#0FFF#0 000 #1FFF8x8 dot pattern

MZ35009) CursorSharp of the cursor: Same as seen in Model 3200 Reverse and blink)10) Light pen inputincorporates the light pen input c

M7 35002) Read/write from Z 80 to VRAM(1) Timing period for display and V-RAM Read/write.H • SYNC-J~L^>-'7 Range wh°ra RDC can draw.Fly back

MZ35004) Graphic VRAM memory (MZIR03)• Block Diagram1. read/wnte ModeThe select signal RASA, RASB and RASC are generate from R AS, A14 and A

MZ35001-2. MZ-1K01 (Keyboard) specificationOutlineMZ1K02 U.S. keyboard (ASCII) MZ1K04 German keyboardMZ1K03: U.K. keyboard (ISO). MZ1K05: French ke

MZ3500(2) 640 X 400 dots display modeOption i {48K byte)B/W: 1 frameColor: 1 frameA #3FFF116KVideo 1V #0000_____1 trT16bitColor can be designated for

Mzasoo(2) 640 X 400 bits display modefH = 20.92 kHz fV = 47.3 HzO--------X : Y : 1 : 1GDC-1 (80 digits) Character display (40 digits)GDC-28 bitsgra

hi'' 3«)0CH48O' For 40 digit display 1 : For 80 digit displayThere is a 40/80 digit switching signal I/O port in the gate ar

M Z 35004Æ. Master slice LSI (CSP-1) SP6102C 002 signal descriptionPm No.PrionlyIN/OUTFunctionSignal Name1HSY.INHorizontal synchronizing signal from t

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MZ35004 6. LSI (CSP 2) SP6012C-003 Signal DescriptionPin NoPolantyIN/OUTFunctionSignal Name1HSY2 INHorizontal synchronizing signal from GDC2 which als

M/3^.00Pm NoPrior llyIN/OUT FunctionSignal Name36M32IN Clock input 32MHz, 200 raster37FSOUT Graphic DRAM address multiplexer signal (High order 8 bits

MZ35004-7. GDC (Graphic display controller) (UPD7220) signal descriptionPin No.PolaritySignal Name2XCCLKDBINHSYNC-REFIN/OUTINOUTOUTFunctionDouble cha

M Z 3500Pm NoPolarity Signal NameIN/OUTFunction35-37AD13(LC0)-AD15(LC2lIN/OUTProvides the following functions based on the operational mode of the GDC

MZ35001-4. MZ-IR03OutlineOptional board used graphic display functions with the Model-3500 series CPU. It includes 32K6 of RAM. It is inserted through

4 8 CG Address Select CircuitASCII C.G. Structure1020 1011-leBytesifiBytes1000OM-I-0020 001 h8 Bytes0018 0017 8 Bytes0010 m 18 Bytes0 I0>' 0

MZ35004 9. VSYNC[Circuit description]When more than two UPD7220 GDC's are to l>e operated in parallel, one must be assigned to

4-10. Character VRAM select circuitMZ3500[Circuit description]With respect to GCD1, the assignment during read/write of the character VIDEO-

MZ35004-12. Read/write from the Z-80 to V RAMRead/write of the Model 3500 V-RAM is done via the UPD7220GDC. There are two methods used

MZ3500(Subroutine lo send command and parameter to the GDC via the FIFO)HL reg — First address of the command code oarameter table. B. reg — Q'ty

MZ3500[Explanation]C - COMMAND CODE 1 To AP_ parameter »Display dot, specify the display address of the VRAM and the dot address. Set th

M 7. 35002) Straight line drawingfjOOOO0028000100270050VRAM 16 bit structureExample to draw a straight line from (X, Y) = (3, 1) to (X,Y) = (635, 1).C

M Z 35005. MFD INTERFACE5-1. OutlineFloppy disk IS a disk which is made of a mylar sheet whose surface is coated with magnetic parti

M Z 3500Example 2: CE330S (light passing through the notchis sensed and decoded as write protect) (Double side, Double density)Write enabledLight IS

MZ3500o MFM method (double density)The MFM method writes data on the basis of the condì tion metntioned below, and it yields a data density

MZ35001-6. MZ-1R06OutlineOptional board for memory expantion of the MZ-3500 sries CPU. with this option the main memory (RAM) can be expanded up to a

M 7 3500Shown below IS an enlarged view of data format sequence Writing starts as soon as the index hole comes through the index dete

5-3. MFD interface block diagramMZ350056 -

5^. FDC (UPD765)UPD765 pin configuration (top view)MZ3500UPD765 block diagramKLSt I 0~---►RDO——►WHO——►CSO—AOO—DBOI NDEXO--------►I NTCV«------)fO-GNDO

UPD765 signal descriptionMZ3500Pin No.Signal nameI/O Function40Vcc-+5V20GND-0V1901Single phase, TTL level clock1RESET Set the FDC into an Idle state,

MZ350CP.n NoSignal nameI/OFunction32. 31PSO. 1Signal used to either advance or delay the write data in writing under the MFM mode, to obtain timing ad

5-7, Precompensate CircuitM 7.3500<ITE DATAPSOPS1FM MFMValue of LSI6300Not changedNot changed110101-LATE(125ps)11001 0 -EARLY(125iis)11101- - -(Tab

In the case of the MFM method, need to trace cycle fluctuation IS further increased, as a peak shift is apt to occur because th

2) VFO circuit configurationMZ3500The VFO circuit has the following capabilities.(1) Two modes; MFM and FM.(2) The VFO circuit operation is sus

M -- 3.1NomaiSTD01MHzOQA) __|~OQB)©.©.©©"To_©~MFM Mode1_Eary©.©.©®"1©__ © —Delay©_©____©___©—63

MZ3500C(QB)D(QC)WINDOWFM mode timing chartA 4MB(QA) J 1______I L_J L_r~LJ“L1_NormalEFLOPAdvancedFLOP1____rDelayedLKQOP1____rrDoes not trace i l^is.64

1-7. MZ-1D07MZ3500OutlineHigh resolution MZ 3500 senes 12 green monitorVideo tubeDisplay capacitySpecificationsDisplay sizeInput signalsPower supplyCa

5-11. Media format0 tr.ick^<¿3500Sector MASTERBLANK MEDIABoot, OS information (See Fig 1)00BOOT00BOOT00BOOT00C5 , D9 . D4 , Cl , D7 . 404000E5 , D6

M/asooTrack 0, sector 1 information (SBACIS) (Fig 1)-------1-------1-------1------1------1-------]-------1-----48'i00'48lo4'02'oo!

М7 350?о Мар informationо track 9 sectorО track 10 sectorFFHI 71!FFHFFH8e>HFFH128 blocks are controlled by one sector.ООН ~ 7FH 80H: End of link

o Block number allocationThe program and data areas are located after Track 2 1 block = 2K bytes (8 sector)MZ3500(Double side) (Single sided)

MZS5006. R232C INTERFACE6-1. General specificationInput/output formatRS-232C bit serial inpul/outputNo of channels1 channelCode usedJIS 7-channe(/JlS

6-3. Block diagram of the interfaceMZ3S00Peripheral6-4. System switch functionsONOFFSW5Causes an error when the ER signal is low or open during data o

MZ35002) Data output controlERROR 101- 73 -

M/ 3S0U3) Data input controlRead one data /Clears the data before \Vthe start of the receive command /74 -

MZ35006-6. 8253 ControlsBaud rate of this interface will be determined by the clock output of the 8253. The 8251 is configured such

MZ3500D0-D7Data BasRXDReceive Data (IN/OUT)WRWrite (IN)RDRead (IN)C/DControl/Data (IN/OUT)D7 ' DOCSChip Select (IN)DSRData Set Ready (IN)DTR Data

1-8. System configuration of Model 3500MZ35006 -

825 1MZ35008 2 5 1chip addresstOOOl/xxxxlINOUT#1XCLKINDSRINin R OUTCTS 1 NrisOUTTXDOUTTXRDY N.C.TXEN.C.TXCINRXDINRXRDY OUTRXCINSYN/BD N.C.2.45MHz cloc

M 7. 35007. PRINTER INTERFACE7-1. Printer interfacing circuitKl)Z80SUBCPUlOKQWRA1AOAS 4 - ASS AS6 AS7 AR Chip S03Ch 1 p ScU’i t Iode rCS 8255KUWRA

7-3. General description of the parallel interfaceThe 8255 is used for the LSI to control the parallel interface. The 8255 can be set in t

7-6. I/O port map8255 ON SUB CPU BUSM / 3500PA7N.DATAS 'PA6DATATi‘A5 DATASPA4 DATA 5PA3OutputDATA48255CÌPA2 DATASPrinterchip address(CX)11 /xxxx]

8-1. Clock circuit1) Schematic8. OTHER INTERFACESM 2 350o2) Clock timing- 81

MZ35003) a^PD1990ACBlock diagram-O DOU'l-<3 ri>Command specificationC2Cl COCommand DescriptionDOUT Data ShiftNote0 00 Register holdHolds 4

8-2. Voice input/output circuitMZ,"500Music output waveform• Tonal signal OUT1• Sustain PC42SC458emitter♦ Speaker output •• 2SC458 collector• GET

M/35008 3. Expansion and interrupt (See 3-(2)-4 for interrupt)1) Options and expansion unitsOptrons not requiring expansion unitMZ 1K01J!S keyboardMZ

M7 35008 4 System SW1 (DIP SW) (User operative through the cabinet bottom)NoSignal nameFunctionPosition PolarityDescriptionSW1SW2ONOFFPrinter selectON

MZ 3500DIP SW(A)DIP SW(B)123412OFFOFFOFF ON ON ONSwitches are set in this manner before shipment of machines this us the single-sided minifloppy disk

MZ35002. SOFTWARE (MEMORY) CONFIGURATIONMemory will be operated under four states of SDO ~ SD3, depending on the hardware and software

M Z 35009, POWER CIRCUIT DESCRIPTION 1. BLOCK DIAGRAM-12VOutput(Block diagram)A. +5V and +12V supplies1. Functionsa. Supply voltage is first re

M 7,35001 +5V^---orJ +12V• VR IS the+5V or+12V adjusting VR.• D3 IS provided to discharge current from Cj after power off.- 88 -

M2 3500c. Power switching circuitAs the signal from the oscillator is amplified through Q7 to Q6 to change current to the transformer

MZ350010. MZ1K01 KEYBOARD CONTROLLER CIRCUIT DESCRIPTION10-1. Specification of keyboard control1) Input BufferCapacity: 64 bytes• Key-in data is

MZS50010-2. Key search timingSingle key entryKeyBoundingSTROBERETURNn n n n_ _ _ _ _ _ _ _ _ _ _ _ _n_ _ _fl_ _ _fl1 Strobe <—5.5ms—M—Sms______n__

MZ 3500Command flag: "0" when succeedeing 8 bits are a key data. "V when it is a command or a graphic control data.D

10-4. Keyboard controller basic flowPower ONM?3500TimerSTART (5mS)93 -

M/350010-5. keyboard controller signal descriptionPINNoPoralitysignalnameIN/OUTFunction1TO IN Output data signal from the sub CPU (D<0)2XT A LI IN

M'Z ?50CType of error(1) MDF 1/F error^ON OFFIsec. '•sec.(2,' SDO read/write error -CD SDO bank alternation error© AD2 bank alternat

Sector 1, Track 0 information 0MZ 35001015AAH1CHTRACKSIDESECTOR I NNO. OF SECTOR111111[TRACK SIDESECTORSECTORN^ \Represent the system mediaTri ve unit

MZ 3500Operational description(1) Upon reset after power on, the main CPU loads the contents of the initial program loader (IPL) into

Mi1) Memory testSub lOCS RAM (4000H-5FFF)Shared RAM (2003H-23FFH)Shared RAM (2440H-27FFH)Above are tested.[Display](1) Normal test ending RA OK: SUB-

MZ3500( Check No. 4 )( Check No. 5 )/<.y ^ Jf -y > K W"H" in red “H” in green “H” in white( Check No. 6 )( Check No. 7 )( Check No. 8

8) ROM-IPLMAIN CPU CHECKER FLOW CHART 1/2MZ35W

S3Si-54Kl=-.*- •MZ3500MAIN CPU CHECKER FLOW CHART 1/2100 -

SUB CPU CHECKER FLOW CHART 1/3M 7^500- 101 -

MZ3500SUB CPU CHECKER FLOW CHART 2/3SUB CPU CHECKER FLOW CHART 3/3Set th* i*mef to 23 hour», 59 fT^tnoie». 58 »«oodi DecefT)b«r 31 ftV on th« dtsp I

MZ 350012. IPL FLOW CHART12-1. MAIN CPU IPL FLOW CHART 1/2(MAIN CPU ^tPL START \/'ITransfer the programin 1000E-to400E-.ROM/RAM test Select me

MZ3500MAIN CPU IPL FLOW CHART 2/2104

12 2. SUB CPU IPL FLOW CHARTMZ-3500ATh« mam CPU will perfofm retrials uni t the mjter media is inserted- 105 -

13-18. PIN CONFIGURATION OF 1C & LSIMZ-3''O074 LS 00Vu 4K A A A') H <A '41lc>JLlI U U LJ U LiJ UlA IB IN A H ZN(M 74 LS