Sharp MZ-3500 User Manual download pdf (Page 20)

M/3S00

MAIN CPU

I/O PORT IN MEMORY MAPPER

ADDKKSS

-\7 A6 A5 A4 A3 A2 Al AO

111110 0

1111110 1

11111110

11111111

HEX

DHUS

El)

1)7

1)4

1 ()

OUT

SKUH

I I

SKI s

MSI

MSO

MA2

MAI

MAO

M02

MOl

MOO

S\\4

S\)3

S'\2

Stt 1

SEC

FD3

FD2

EDI

SKDY

SACK

1 NP2

INPl

1 NPO

MF2

ME 1

SRQ Bus request from the main CPU to the sub-CPU

Sub-CPU reset signal

Memory system define

Bank select signal to memory area of COOO-FFFF.

Bank select signal to memory area of 2000-3FFF.

System assign switch

FD assign

t. ^------------------------------------------

TÌ1 Sub-CPU READY signal

V Sub-CPU acknowledge signal

Interrupt status

(SW8)

1. All output signals are reset to low level upon power on,

' except for SRBQ that goes high.

2. Noted with a star mark "A" are input/output signals, and

rest of others are processed in the LSI.

#1 I/O port output of MEI and ME2 uses the memory at

the addresses.

( ME2-^8000~ BFFF

1 MEI ^4000 ~7FFF

_____

When MEI and ME2 are in high state, RSAB (RASA) is

inhibited during memory addresses in RAM-A that

correspond to overlayed addresses for ME! and ME2

This is not true during SDÌ mode.

‘ VK IN MEMCKT MM I Mf

M I TO ENCODMf

<*nriT M(t»M FNCODFK

MFH noh

IMP 112h

ii3h 1T4H

IM 2

—

IM «

IMH

1 TsTTiT

IMI

IN=Tt INF?

JNT3

INT4 Tvf

, X 1

X X

1 1 L

1 H

f " ÌLtT“

X X

X X tl

X X

1 " i "

M 1 X

H L

” -J

, " 1 '

H H

H M

■ ^ ■

H H

L H L

FkoM SI Ml

I h <• 11

Wait timing generator

WAIT IS issued once per main CPU fetch cycle.

Its outui IS tri state

TO MAIN Cl I

- 23 -

1 2 ... 15 16 17 18 19 20 21 22 23 24 25 ... 115 116

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Sharp MZ-3500 User Manual Page 20

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