Sharp MZ-3500 User Manual Page 36
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MZ3500
4 6. LSI (CSP 2) SP6012C-003 Signal Description
Pin No
Polanty
IN/OUT
Function
Signal Name
1
HSY2 IN
Horizontal synchronizing signal from GDC2 which also becomes the refresh tirniny .lynoi in tliC'
dynamic RAM mode.
2
BLK2 IN
Erase signal input from the GDC2 which is supplied 4T the following times:
1. Horizotal flyback period.
2. Vertical flyback period.
3. Period from the execution of the SYNC SET command to execution of the DtSP START
command.
4. Line drawing period.
3
DWE
OUT
WRITE ENABLE output for the graphic dynamic RAM.
4 ' 5
AD14-AD15
IN
Input of the display output signals {AD14, ADI 5) from GDC2.
(Used to create DBIA-DBIC in the CSP-2.)
6
DBI2
IN
Input from the GDC2 by which the image memory output is sent on the data bus.
(Used to create RASA-RASC, CAS, PS, DWE in the CSP-2.)
7
DBI1
IN
Input from the GDC1 by which the image memory output is sent on the data bus.
(Used to create BUSG, SOE, SWE in the CSP-2.)
8
BUSG
OUT
Gate signal of the bidirection bus buffer (LS245) which is used to read/wnte attribute, and character,
data from the static RAM (2114A-1,6116P-3).
9
SOE
OUT
OUTPUT ENABLE for character static RAM (6116P-3).
10
SWÉ
OUT
WRITE ENABLE for attribute, character static RAM.
1 1
0816 OUT
8-bit/word and 16-bit/word select signal.
(8-bit/word chosen with LDA, ООН OUT#5D, and 16-bit/word is chosen with LDA, 01 H OUTi?5D.)
12 RASI
IN
Memory control siqnal RAS from GDC1.
(Used to create CGOE, SL1 in CSP-2.)
13 RAS2
IN
Memory control signal RAS from CDC3.
(Used to create §L27 LOAD, RASA-RASC, CAS, PS, DBIA-DBIC, DSP2 in CSP-2.)
14
AS3
IN
Address bus input from the sub-CPU (ASS = AB3)
15
NWRO
IN
Chip select (OUT#5X) of the I/O port in CSP-2.
16-17 DS0-DS1
IN
Data bus input from the sub-CPU (DSO = DBO, DS1 = DB1).
18 RA40
IN
The signal that goes to high level (input from CSP-1) when the 400-raster CRT is connected.
(Used for clock frequency selection in CSP-2.)
19
M40 IN
Clock input from the clock generator (39.32MHz, for 400-raster mode.)
20 GND
IN
OV supply
21
SL2
OUT
Graphic ORAM output paraliel/serial converter 1C 74LS166 shift load signal.
22 RASA
OUT
Graphic DRAM (A), (B) RAS signal.
23
2CM2
OUT
Double character clock output. In the character display mode, a single phase clock of the half the
one character wide frequency is supplied. In the graphic display mode, a single phase clock of
8/16 dot frequency is supplied to GDC2.
24
LOAD
OUT
Graphic DRAM output paraliel/serial converter 1C 74LS166 load timing clock.
25 Vcc
IN
+5V supply.
26
FYD2 OUT
Graphic DRAM output paraliel/serial converter 1C 74LS166 shift out clock.
27
2CK1
OUT
Double character clock output same as 2CK2. In the character display mode, a single phase clock
of one half the one character wide frequency is supplied to GDC1.
28
SL1
OUT
Character CG output paraliel/serial con>^rter 1C 74LS166 shift out clock.
29
SL1
OUT
Character CG output paraliel/serial converter 1C LS166 shift load signal.
Character CG address.
30
CGOE
OUT
Character CG output enable signal.
31-33
DB1C-DB1A
OUT
Timing signal by which the graphic DRAM output is sent on the data bus.
34-35
RAS-C -
RAS-B
OUT
Graphic DRAM RAS (ROW ADDRESS SELECT) siqnal.
RAS-B; RAM(C), (D) RAS-C; RAM (E), (F)
- 41 -
- SERVICE MANUAL 1
- 1. SPECIFICATIONS 2
- Keyboard layout 3
- 1-3. MZ-1U02 3
- 1-4. MZ-IR03 4
- 1-6. MZ-1R06 5
- 1-7. MZ-1D07 6
- 2-1. SDO (INITIALIZE STATE) 8
- MAIN CPU 8
- M* )S V 1 M/} 9
- MZS.'tOO 10
- 2.3. SD2 (ROM based BASIC) 11
- Operational description 12
- 3. CPU AND MEMORY 13
- L© 'MTR ! 14
- 3-3. Sub CPU and I/O port 15
- 1) Block diagram 16
- ‘ VK IN MEMCKT MM I Mf 20
- 4. CRT DISPLAY 22
- X 25 lines screen.) 24
- For Model 3200 senes 26
- 4-2. Video RAM 27
- 5) Synchronize signal timing 30
- X : Y - 1 : 2 30
- X : Y : 1 : 1 31
- 'iBK byte 32
- (option I) 32
- 48K byte 32
- (option tl) 32
- M Z 3500 34
- CSP 2 Block Diagram 37
- 20 GND IN 38
- ASCII C.G. Structure 40
- 4 9. VSYNC 41
- ARIO = HI 42
- > FIFO Empty? 44
- [Explanation] 45
- Straight line drawing 46
- Whereas 46
- 5. MFD INTERFACE 47
- ^ 0 ^ 0 1 49
- 8) Data write procedure 50
- 5^. FDC (UPD765) 52
- UPD765 signal description 53
- 5-5. Data recording method 54
- <ITE DATA 55
- Write pulse [] fl d fl R 56
- Polarity inversion 56
- +5V RtAD DATA 57
- M -- 3.1 58
- ©"T 58
- Advanced 59
- Does not trace i l^is 59
- 5-11. Media format 60
- (Bbyles) 61
- 02 0\ FF FF 62
- ( 2KX 152 = 304K ) 63
- Stop bit 64
- 6-4. System switch functions 65
- 6-5. 8251AC controls 65
- 2) Data output control 66
- 3) Data input control 67
- 7-D0C># 68
- 3iil>CPU of Ni^ 70
- <i> 71
- 7 4. Data transfer timing 72
- 7-6. I/O port map 73
- 8. OTHER INTERFACES 74
- -<3 ri> 75
- MZ,"500 76
- DIP SW(A) 79
- 1. BLOCK DIAGRAM 80
- A. +5V and +12V supplies 80
- M 7,3500 81
- 3. Alarm circuit 82
- DESCRIPTION 83
- 10-2. Key search timing 84
- JLJl_JlJT_ri_rLJl 85
- Power ON 86
- START (5mS) 86
- 11. SELF CHECK FUNCTIONS 87
- CD SDO bank alternation error 88
- 11-2. Sub-CPU side 89
- .8 test the 90
- 20 lines 90
- /<.y ^ Jf -y > K W 91
- 8) ROM-IPL 92
- S3Si-54Kl=-.*- • 93
- 12. IPL FLOW CHART 96
- MAIN CPU IPL FLOW CHART 2/2 97
- 12 2. SUB CPU IPL FLOW CHART 98
- ■ I I Y Y TV 99
- IjJliJlJjljJljJLllLljLLJ 99
- LlJ LiJ LiJ Lei LiJ LLl LiJ 99
- LJLeJ'LDliJLiJLLjLJLiJ 99
- Pi co vO co fO Pi 100
- Ч Г ^n UO 100
- ¿. ^ О 101
- Û. CM Û 101
- GUIDE LIST 102
- I'l Exteriors 103
- 1 Exteriors 104
- PWB & Fixing angles 105
- [3 Connector 106
- [4] Others 107
- 5 CPU PWB 107
- 5I CPU PWB 108
- U Power supply unit 108
- [6j Power supply unit 109
- П MZ1R06 (RAM board) 111
- SHARP CORPORATION 116
- Industrial Instruments Group 116
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