Sharp ER-A770 Service Manual download pdf (Page 50)

6. Pseudo SRAM (Standard)

The device is a TOSHIBA 4MB SRAM (TC51V8512AFT 512K 8bit)

with an access time of 120ns.

6-1. CPU interface

The figure below shows a typical pseudo SRAM interface in the ER-

A770.

6-2. Pseudo SRAM address

Standard SRAM is decoded as follows by the RASPN1 signal.

700000h ∼ 7FFFFFh

The base signal is 2MB. It thus wraparounds with 600000H ∼

6FFFFFH 1MB.

Pseudo SRAM consists of 1 chip for respective even and odd number

addresses. Both of word and byte access from CPU are available.

7. NOR-type flash memory

Here is the explanation for the interface of NOR-type flash memory.

The device is Sharp’s LH28F016SU flash memory which consists of

512 K words × 16 or 1 MB × 8, with 32 blocks of 64 KB.

7-1. CPU interface

The figure below shows a typical interface for the LH28F016SU of the

ER-A770 system.

7-2. Device control

After resetting, the device automatically enters the array read mode

and perform the same action as the usual ROM, thus requiring no

special consideration when reading data.

Data can be written at high speed by using the page buffer.

8. SSP control

The ER-A770 uses flash memory in the place of EPROM, so it is

possible to rewrite the contents of the flash memory in changing the

program. However, since the existing gate array MPCA8 is used, it is

also possible to use the conventional SSP.

8-1. Operation

Like the MPCA7, the MPCA8 adopts the break address register com-

parison method for detecting addresses. The operation of this method

is briefly explained below.

The gate array always compares the break address register (BAR)

built in the gate array, with the address bus to monitor the address

bus.

If both agree, the gate array outputs the NMI signal to the CPU, which

in turn shifts from normal handling to exception handling.

In both the MPCA7 and the MPCA8, SSP is achieved by the above

operation.

The setting of the break address register (BAR) is directly written in

the addresses from FFFF00h to FFFFFFh.

9. Interrupt control

There are roughly two types of interrupts:

• Internal interrupts: Controlled inside the CPU

• External interrupts: Input into the CPU from outside

9-1. Internal interrupts

Device interrupts built in the CPU are used for the following applica-

tions:

Event factor Application

SC11 Interrupt source as RS232 : CH8

SC12 Not used (SC1 is used for CKDC interface.)

FRT1 (ICI)

(OCRA)

(OCRB)

(OVF)

INTMCR ∼ MCR interrupt (to FT11 terminal)

FRT2 (ICI) Standard SHEN event (for CKDC)

(OCRA) Simple IRC timer event

(OCRB) RS232 timer event

(OVF) System timer (53 ms)

TMR (CMA)

(CMB)

(OVF)

WDT (OVF) Drawer open timer

A/D Not used

NMI SSP request

9-2. External interrupts

The following types of external interrupts are available:

• NMI (SSP)

• IRQ0 (Standard I/O interrupt)

• IRQ1 (RS232 interrupt)

• IRQ2 (Not Used)

• IRQ3 (Used as SCK terminal)

Odd side PSRAM

/OWR

/HWR

/LWR

/RESET

/AS

/PCE1_O

/WSWAP

D7~D0

D15~D8

/WR

/CE

SD7~SD0

EVEN sid e PSRAM

Gate Arra y

RASPN1

/RESET

/AS

/PCE1_E

/HWR

SD7~SD0

/WR

/CE

RASPN1E

RASPN1

/OE

/REFSH

RASPN1

RASPN2

/RASPN12

ISP2032

/RSWAP

REFSH

/RD

CLK

CLR

/PR

Fig. 8

RESET-

FVPON

NORDY

H8/510

DATA

RD-

PORT64

PORT63

MPCA8

FROS1-

WE#

OE#

CE0#

GND

VPP

CE1#

RP#

3/5#

VCC

BYTE#

RY/BY#

A0~A2

DQ0~DQ1

WP#

LH28F

016SUT

ADDRES

HWR-

1 2 ... 45 46 47 48 49 50 51 52 53 54 55 ... 88 89

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