Sharp ER-A770 Service Manual Page 49

  • Download
  • Add to my manuals
  • Print
  • Page
    / 89
  • Table of contents
  • BOOKMARKS
  • Rated. / 5. Based on customer reviews
Page view 48
3-6. Extended I/O area
The addresses from F00000h to FFFFFFh are called an extended I/O
area. The ER-A770 uses the following addresses as the break ad-
dress register (BAR) for SSP.
FFFF00h FFFFFFh
4. LCD display
The ER-A770 uses a 320 x 240 dot monochromatic LCD for the main
display and VGAC (MN89303A) for the display controller which is
connected to H8/510 in the ISA bus connection mode.
4-1. Block diagram
Here is the block diagram of the LCD and its allied components.
4-2. LCD panel
The LCD panel uses a dot-matrix liquid crystal module LM320153
with monochromatic STN and COFT backlight. The resolution is 320
x 240.
4-3. Display controller
Matsushita VGAC (MN89303A) is used for display controller.
VRAM is on the address space of the CPU and data can be written
on and read from it by every 128 KB of bank at the address C00000H
C1FFFFH from the CPU side. VRAM consists of 4 banks.
4-4. LCD ON control
The LCD’s is bias power supply is controlled by the MN89303A termi-
nal LCDON to turn the LCD screen on and off.
The LCDON is at "L" at resetting +5V power is supplied to the LCD by
setting the expanded function control register bit5 of MN89303A to
"H" with software. The LCD screen isn’t turned on until +5V is sup-
plied.
4-5. Back light control
The back light is turned ON/OFF by the MN89303A terminal
BACKON. The initial value is "L" and the back light is off. By setting
the expanded function control register bit6 of MN89303A to "H", the
inverter unit is turned on.
4-6. Luminance and contrast adjustment
Luminance: Luminance is adjusted with an inverter which has dim-
ming function.
Contrast: Contrast is adjusted by controlling the contrast adjust-
ment voltage (VCON) of the LM320153
5. Customer display
The ER-A770 can incorporate a UP-I16DP (display tube unit for the
UP-P16DP) for the customer display to carry out the same control as
for the pole display (UP-P16DP).
CPU
H8/510
RD#
WR#
SD0-15
SA0-16
IORD#
MEMRD#
IOWR#
MEMWR#
PHAI CLK
WAIT#
RAS/CAS
WE#
MD0-15
MA0-9
RAS/CAS
WE#
D0-15
A0-9
VRAM
DRAM:512KB
LD0-3
LP
FP
DCLK
LD0-3
LP
FP
DCLK
LCD (320X240)
BACKLIGHTVEE
BIAS
INVERTER
LCDON
BACKON
LCDWT
RFSH#
WAIT#
MPCA8
MN89303A
Fig. 7
Page view 48
1 2 ... 44 45 46 47 48 49 50 51 52 53 54 ... 88 89

Comments to this Manuals

No comments