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3) General description

The CPUs are fourth-generation enhanced microprocessors with ex-

ceptional computational power. They offer higher system throughput

and more efficient memory utilization than comparable second- and

third-generation microprocessors. The internal registers contain 208

bits of read/write memory that are accessible to the programmer.

These registers include two sets of six general-purpose registers

which may be used individually as either 8-bit registers or as 16-bit

registers. A group of "Exchange" instructions makes either set of

main or alternate registers accessible to the programmer. The alter-

nate set allows operation in foreground/background mode or it may

be reserved for very fast interrupt response.

The CPU also contains a Stack Pointer, Program Counter, two index

registers, a Refresh register (counter), and an Interrupt register. The

CPU is easy to incorporate into a system since it requires only a

single +5V power source. All output signals are fully decoded and

timed to control standard memory or peripheral circuits; the CPU is

supported by an extensive family of peripheral controllers.

The internal block diagram (Figure 3) shows the primary functions of

the processors. Subsequent text provides more detail on the I/O con-

troller family, registers, instruction set, interrupts and daisy chaining,

and CPU timing.

4) Pin description

No.

Symbol

Signal

name

In/Out Function

1 CLK CLK In Clock

2 D4 S D4 In/Out Data bus

3 D3 S D3 In/Out Data bus

4 D5 S D5 In/Out Data bus

5 D6 S D6 In/Out Data bus

6+5V VCC —+5V

7 D2 S D2 In/Out Data bus

8 D7 S D7 In/Out Data bus

9 D0 S D0 In/Out Data bus

10 D1 S D1 In/Out Data bus

11 NC NC — NC

INT S INT In Interrupt request signal

NMI VCC —

Non-maskable interrupt

signal

HALT VCC — +5V

MREQ S MRQ Out Memory request signal

IORQ S IORQ Out Input / Output request signal

17 NC NC — NC

No.

Symbol

Signal

name

In/Out Function

RD S RDS Out Rread signal

WR S WRS Out Write signal

BUSAK BUSAK Out Bus acknowledge signal

WAIT S WAIT In Wait signal

BUSRQ BUSRQ In Bus request signal

RESET S RES In Reset signal

M1 S M1 Out Machine cycle one signal

RFSH NC — NC

26 GND GND — GND

27 A0 S A0 Out Address bus

28 A1 S A1 Out Address bus

29 A2 S A2 Out Address bus

30 A3 S A3 Out Address bus

31 A4 S A4 Out Address bus

32 A5 S A5 Out Address bus

33 NC NC — NC

34 A6 S A6 Out Address bus

35 A7 S A7 Out Address bus

36 A8 S A8 Out Address bus

37 A9 S A9 Out Address bus

38 A10 S A10 Out Address bus

39 NC NC — NC

40 A11 S A11 Out Address bus

42 A13 S A13 Out Address bus

43 A14 S A14 Out Address bus

44 A15 S A15 Out Address bus

2-5. Z80 CTC

1) Features

• Four independently programmable counter/timer channels, each

with a readable downcounter and a selectable 16 or 256 prescaler.

Downcounters are reloaded automatically at zero count.

• Selectable positive or negative trigger initiates timer operation.

• Three channels have Zero Count/Timeout outputs capable of driv-

ing Darlington transistors. (1.5mV @ 1.5V)

• NMOS version for cost sensitive performance solutions.

• CMOS version for the designs requiring low power consumption

• NMOS Z0843004 - 4 MHz, Z0843006 - 6.17 MHz.

• CMOS Z84C3006 - DC to 6.17 MHz, Z84C3008 - DC to 8 MHz,

Z84C3010 - DC to 10 MHz

• Interfaces directly to the Z80 CPU or—for baud rate generation—

to the Z80 SIO.

• Standard Z80 Family daisy-chain interrupt structure provides fully

vectored, prioritaized interrupts without external logic. The CTC

may also be used as an interrupt controller.

• 6 MHz version supports 6.144 MHz CPU clock operation.

2) General description

The Z80 CTC, hereinafter referred to as Z80 CTC or CTC, four-chan-

nel counter/timer can be programmed by system software for a broad

range of counting and timing applications. The four independently

programmable channels of the Z80 CTC satisfy common microcom-

puter system requirements for event counting, interrupt and interval

timing, and general clock rate generation.

System design is simplified because the CTC connects directly to

both the Z80 CPU and the Z80 SIO with no additional logic. In larger

systems, address decoders and buffers may be required.

INTERNAL DATA BUS ALU

ARRAY

ADDRESS

LOGIC AND

BUFFERS

16-BIT

ADDRESS BUS

8-BIT

DATA BUS

INSTRUCTION

DATA BUS

INTERFACE

INSTRUCTION

DECODER

CPU

TIMING

CPU

TIMING

CONTROL

+5V

GND

CLOCK

8 SYSTEMS

AND CPU

CONTROL

OUTPUTS

5 CPU

CONTROL

INPUTS

Figure 3. Z80C CPU Block Diagram

1 2 ... 34 35 36 37 38 39 40 41 42 43 44 ... 88 89

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