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4-24 Intel
®
StrongARM
®
SA-1110 Microprocessor Development Board
User’s Guide
Hardware Considerations
wired in parallel with a MIC5219 3.3V LDO which is powered directly from the battery. The
MIC5219 has a very low drop out voltage, has an enable input, and is available in very small
packaging.
With the two LDO outputs wired in parallel, the load is powered from the LDO that has the highest
output voltage. As long as the battery is above 3.45 V, the MIC5219 3.3 V LDO powers the 3.3 V
circuits on the SA-1110 Development Board. If the battery sags below 3.45 V, then the 3.3 V
circuits smoothly transition to drawing powered from the 3.2 V LDO in the MAX1705 which is
powered from the main 5.5 V output of the MAX1705 boost regulator. This bootstrap feature
allows the 3.2 V LDO to pick up or bootstrap the 3.3 V circuits when the battery sags below 3.45 V
necessary to power the 3.3 V LDO. Setting the MAX1705 LDO to 3.2 V allows a smooth
automatic load transfer from the MIC5219 3.3V LDO when the battery voltage sags under heavy
load from the radio transmitter or when the battery is near the end of charge and the battery voltage
is sinking below 3.45 V. This method allows the SA1110 Development Board to use the very
efficient and clean direct battery powered 3.3 V LDO through 80% of the discharge cycle while
providing reserve boosted linear regulation for the 3.3 V circuits when the battery drops below
3.45 V. All the 3.3 V devices in the SA-1110 Development Board are specified to function
normally down to 3.0 V, so the 3.3 V to 3.2 V switch over still has 200 mV of voltage margin.
The 3.2 V LDO reserve boost regulation power supply is no more then 52% efficient when the
boost output is at 5.5 V. However, this supply is only used when the radio is transmitting at full
power, which may cause the battery to sag below 3.45 V. In this case, the power drain from the
radio is almost 10 times the entire 3.2 V load anyway, making the poor 3.2 V conversion efficiency
while transmitting inconsequential.
The third feature of the MAX1705 used in the SA-1110 Development Board power system is the
battery threshold sensing circuit. This circuit is set to detect the Li-ion battery going below the
2.7 V end of charge threshold. The low battery output signal, BATT_LOCKOUT, forces the
MAX1705 to shut down and also shuts down the MIC5219 3.3V linear regulator, which shuts
down the SA-1110 and all other 3.3 V loads including SDRAM. When the SA-1110 is shut down,
the SA_PWR_EN signal goes low which also shuts down the MAX1692 1.5 V core regulator. The
end result is all battery loads are off, all memory contents are lost, but the expensive Li-ion battery
is saved from over discharge damage that can drastically reduce its storage capacity.
4.11.2.1 Sleep Mode
The efficiency of the 3.3 V power system is very critical in sleep mode. The SA-1110 Development
Board with its two SDRAM memories requires about 1 mA sleep current on the 3.3 V rail. With a
100% efficient 3.3 V power conversion, a 1000 mah battery fully charged results in about 1000
hours of sleep time, or about 6 weeks. A power system that boosts the Li-ion battery voltage to 5 V
and then bucks it to 3.3 V (less than 65% efficient) would last less then 4 weeks.
The efficiency of the 3.3 V rail in sleep mode with the linear boost bootstrap design is over 91% for
most of the battery discharge cycle and approaches 100% towards the 3.32 V drop out point. This
efficiency is better than any switching regulator can achieve in low-power mode. Below the 3.32 V
drop out point, with the MAX1705 in track mode and its 3.2 V LDO regulator picking up the load,
the combined efficiency of the boost regulator in low-power PFM and track mode and the 3.2 V
LDO is 0.8 X 3.2/3.5 X 100 = 73%. However this 73% only applies to the last 10% of the discharge
cycle where the battery voltage is below 3.32 V and before it falls to the 2.7 V battery lockout cut-
off point.
- StrongARM 1
- SA-1110 1
- Microprocessor Development 1
- Contents 3
- StrongARM 4
- 1.1 Related Documentation 10
- Introduction 11
- Getting Started 13
- Theory of Operation 25
- Hardware Considerations 29
- 4.2.2 Flash 30
- 4.3 Intel 32
- SA-1110 GPIO Usage 32
- 4.3.1 GPIO 0 and GPIO 1 34
- 4.3.2 Intel 35
- SA-1110 GPIO Pin Descriptions 35
- 4.4 Register Descriptions 36
- 0x1200,0000 38
- 4.5 System Reset 43
- 4.6 System Displays 43
- 4.6.1 LED Displays 44
- 4.6.2 LCD Displays 44
- 4.7 Debugging 45
- 4.7.2 Debug Switches 46
- 4.7.3 Function Switches 46
- 4.7.4 Logic Analyzer Support 46
- 4.8 SMBus 47
- 4.9 Serial Ports 47
- 4.10 Power System 48
- 4.10.2.1 1.5V Core Power 49
- Development Board 50
- Regulator 51
- 4.11.2.1 Sleep Mode 52
- 4.11.2.4 Radio Power 54
- 4.12 Audio Systems 56
- 4.12.1 Stereo Codec 57
- 4.12.2 L3 Bus 57
- 4.12.3 Stereo Codec Interface 58
- 4.12.4 Microphone and Speaker 59
- 4.13 Radio Interface 61
- 4.14 Quiet Alert Motor 62
- 4.16 USB Slave Port 63
- Analog I/O 65
- 5.1.2 Battery Temperature 66
- 5.1.3 Analog Spare 66
- 5.2 Analog Outputs 67
- 5.3 Touch Screen 67
- System Power Management 69
- System Power Management 70
- 6.2.4 Battery Capacity 71
- 6.2.5 Battery Safety 71
- 6.2.6 Fuel Gauging 72
- • Max charge current 73
- • Max temp 73
- CPLD Code A 75
- CPLD Code 76
- A.2 LCD_P2.PHD File Contents 79
- In-Circuit Programming B 89
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